IDT72V36104 查看數據表（PDF） - Integrated Device Technology

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IDT72V36104

3.3 VOLT CMOS SyncBiFIFO™ WITH BUS-MATCHING

Integrated Device Technology 

IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFOTM WITH

BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65 and 536 x 36 x 2

CLKA

1

2

3

4

COMMERCIAL TEMPERATURE RANGE

CLKB

1

2

3

4

ENB

tRSTS

RT1

tRTMS

tRSTH

tRTMH

tENS2

tENH

RTM

EFB

(2)

tREF

(2)

tREF

B0-Bn

tA

Wx

W1

4677 drw31

NOTES:

1. CSB = LOW

2. Retransmit setup is complete after EFB returns HIGH, only then can a read operation begin.

3. W1 = first word written to the FIFO1 after Master Reset on FIFO1.

4. No more than D-2 may be written to the FIFO1 between Reset of FIFO1 (Master or Partial) and Retransmit setup. Therefore, FFA will be LOW throughout the Retransmit

setup procedure. D = 16,384, 32,768 and 65,536 for the IDT72V3684, IDT72V3694 and IDT72V36104 respectively.

Figure 29. Retransmit Timing for FIFO1 (IDT Standard Mode)

CLKB

1

2

3

4

CLKA

1

2

3

4

ENA

tRSTS

RT2

tRTMS

tRSTH

tRTMH

tENS2

tENH

RTM

EFA

A0-An

(2)

tREF

Wx

(2)

tREF

tA

W1

4677 drw32

NOTES:

1. CSA = LOW

2. Retransmit setup is complete after EFA returns HIGH, only then can a read operation begin.

3. W1 = first word written to the FIFO1 after Master Reset on FIFO2.

4. No more than D-2 may be written to the FIFO1 between Reset of FIFO2 (Master or Partial) and Retransmit setup. Therefore, FFB will be LOW throughout the Retransmit setup

procedure. D = 16,384, 32,768 and 65,536 for the IDT72V3684. IDT72V3694 and IDT72V36104 respectively.

Figure 30. Retransmit Timing for FIFO2 (IDT Standard Mode)

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