IDT72V3642L15PF 查看數據表（PDF） - Integrated Device Technology

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IDT72V3642L15PF

3.3 VOLT CMOS SyncBiFIFO 256 x 36 x 2 512 x 36 x 2 1/024 x 36 x 2

Integrated Device Technology 

IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

CLKB

CSB

tCLK

tCLKH

tCLKL

LOW

W/RB

MBB

ENB

HIGH

LOW

tENS2

tENH

EFB

B0-B35

CLKA

HIGH

tA

Previous Word in FIFO1 Output Register

tSKEW1(1)

tCLK

tCLKH

tCLKL

1

FFA

CSA

FIFO1 Full

LOW

COMMERCIAL TEMPERATURE RANGE

Next Word From FIFO1

2

tWFF

tWFF

W/RA

MBA

ENA

A0-A35

HIGH

tENS2

tENS2

tENH

tENH

tDS

tDH

Write

To FIFO1

4660 drw 15

NOTE:

1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising

CLKA edge is less than tSKEW1, then FFA may transition HIGH one CLKA cycle later than shown.

Figure 13. FFA Flag Timing and First Available Write when FIFO1 is Full (IDT Standard Mode)

22

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