IDT72V801L20TFI 查看數據表（PDF） - Integrated Device Technology

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IDT72V801L20TFI

3.3 VOLT DUAL CMOS SyncFIFO™

Integrated Device Technology 

IDT72V801/72V811/72V821/72V831/72V841/72V851

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

WCLKA

(WCLKB)

DA0 - DA8

(DB0 - DB8)

FFA (FFB)

WENA1

(WENB1)

WENA2

(WENB2)

(If Applicable)

NO WRITE

tSKEW1

tDS

tWFF

tENS

tENS

tDH

tWFF

tENH

tENH

NO WRITE

tSKEW1

NO WRITE

tWFF

tENS(1)

tENS(1)

RCLKA

(RCLKB)

tENS

RENA1

(RENB2)

OEA LOW

(OEB)

tENH

tA

QA0 - QA8

(QB0 - QB8)

DATA IN OUTPUT REGISTER

tENS

tENH

tA

DATA READ

NOTE:

1. Only one of the two Write Enable inputs, WEN1 or WEN2, needs to go inactive to inhibit writes to the FIFO.

NEXT DATA READ

4093 drw 10

Figure 8. Full Flag Timing

WCLKA (WCLKB)

DA0 - DA8

(DB0 - DB8)

tDS

tENS

DATA WRITE 1

tENH

WENA1, (WENB1)

tENS

WENA2 (WENB2)

(If Applicable)

RCLKA (RLCKB)

tENH

tSKEW1

(1)

tFRL

tREF

EFA (EFB)

tDS

tENS

DATA WRITE 2

tENH

tENS

tENH

tREF

tSKEW1

(1)

tFRL

tREF

RENA1, RENA2

(RENB1, RENB2)

OEA (OEB) LOW

tA

QA0 - QA8

(QB0 - QB8)

DATA IN OUTPUT REGISTER

NOTE:

1. When tSKEW1 ≥ minimum specification, tFRL maximum = tCLK + tSKEW1

When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1

The Latency Timings apply only at the Empty Boundary (EFA, EFB = LOW).

Figure 9. Empty Flag Timing

11

DATA READ

4093 drw 11

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