IDT723636(2014) 查看數據表（PDF） - Integrated Device Technology

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IDT723636
(Rev.:2014)

CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 1,024 x 36 x 2

Integrated Device Technology 

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™

WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

CLKC

WENC

CLKA

tEtNESN2S2

AEA X2 Words in FIFO2

tENH

tSKEW2(1)

1

2

tPAE

tPAE

(X2+1) Words in FIFO2

tENS2

tENH

ENA

NOTES:

3271 drw26

1. tSKEW2 is the minimum time between a rising CLKC edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKC edge

and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.

2. FIFO2 Write (MBC = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.

3. If Port C size is word or byte, tSKEW2 is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively.

Figure 25. Timing for AEA when FIFO2 is Almost-Empty (IDT Standard and FWFT Modes)

CLKA

ENA

tENS2

AFA [D-(Y1+1)] Words in FIFO1

tENH

tPAF

(1)

tSKEW2

1

(D-Y1) Words in FIFO1

2

tPAF

CLKB

tENS2

tENH

RENB

NOTES:

3271 drw27

1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge

and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKA cycle later than shown.

2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.

3. D = Maximum FIFO Depth = 256 for the IDT723626, 512 for the IDT723636, 1,024 for the IDT723646.

4. If Port B size is word or byte, tSKEW2 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.

Figure 26. Timing for AFA when FIFO1 is Almost-Full (IDT Standard and FWFT Modes)

CLKC

tENS2

tENH

WENC

tPAF

AFC [D-(Y2+1)] Words in FIFO2

(1)

tSKEW2

1

(D-Y2) Words in FIFO2

2

tPAF

CLKA

tENS2

tENH

ENA

NOTES:

3271 drw28

1. tSKEW2 is the minimum time between a rising CLKC edge and a rising CLKA edge for AFC to transition HIGH in the next CLKC cycle. If the time between the rising CLKC edge

and rising CLKA edge is less than tSKEW2, then AFC may transition HIGH one CLKC cycle later than shown.

2. FIFO2 write (MBC = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.

3. D = Maximum FIFO Depth = 256 for the IDT723626, 512 for the IDT723636, 1,024 for the IDT723646.

4. Port C size is word or byte, AFC is set LOW by the last word or byte write of the long word, respectively.

Figure 27. Timing for AFC when FIFO2 is Almost-Full (IDT Standard and FWFT Modes)

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