IDT723651L20(2002) 查看數據表（PDF） - Integrated Device Technology

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IDT723651L20
(Rev.:2002)

CMOS SyncFIFO™ 512 x 36 1,024 x 36 2,048 x 36

Integrated Device Technology 

IDT723631/723641/723651 CMOS SyncFIFO™

512 x 36, 1,024 x 36 and 2,048 x 36

CLKA

4

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

RST

IR

FS1/SEN

tFSS

tFSS

tSPH

tFSH

tSENS

tSDS

tSENH

tSDH

tSENS

tSDS

tSENH

tSDH

FS0/SD

AF Offset

(Y) MSB

AE Offset

(X) LSB

NOTE:

1. It is not necessary to program Offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IR is set HIGH.

Figure 4. Programming the Almost-Full Flag and Almost-Empty Flag Offset Values Serially

tPIR

3023 drw07

CLKA

tCLKH

tCLK

tCLKL

IR HIGH

CSA

W/RA

MBA

ENA

A0 - A35

tENS2

tENS2

tENH2

tENH2

tENS2

tENH2

tENS1

tENH1

tENS1

tENH1

tDS

tDH

W1

W2

Figure 5. FIFO Write Cycle Timing

tENS1

tENH1

No Operation

3023 drw08

CLKB

tCLKH

tCLK

tCLKL

OR HIGH

CSB

W/RB

MBB

ENB

B0 - B35

tENS1

tENH1

tENS1

tENH1

tMDV

tEN

tA

W1

tA

W2

Figure 6. FIFO Read Cycle Timing

14

tENS1

No Operation

W3

tENH1

tDIS

3023 drw09

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