IDT723631(2002) 查看數據表（PDF） - Integrated Device Technology

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IDT723631
(Rev.:2002)

CMOS SyncFIFO™ 512 x 36 1,024 x 36 2,048 x 36

Integrated Device Technology 

IDT723631/723641/723651 CMOS SyncFIFO™

512 x 36, 1,024 x 36 and 2,048 x 36

CLKA

CLKB

RST

tRSTS

FS1,FS0

tPIR

IR

OR

AE

AF

MBF1,

MBF2

tRSF

tRSF

tRSF

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

tFSS

tRSTH

tFSH

0,1

tPIR

tPOR

3023 drw05

Figure 2. FIFO Reset Loading X and Y with a Preset Value of Eight

CLKA

4

RST

tFSS

FS1,FS0

tFSH

IR

ENA

A0 - A35

tPIR

tENS1

tENH1

tDS

tDH

AF Offset

(Y)

AE Offset

(X)

NOTE:

1. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program Offset register on consecutive clock cycles.

First Word

Stored in FIFO

3023 drw06

Figure 3. Programming the Almost-Full Flag and Almost-Empty Flag Offset Values from Port A

13

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