IDT72201L25JGI(2017) 查看數據表（PDF） - Integrated Device Technology

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IDT72201L25JGI
(Rev.:2017)

CMOS SyncFIFO™ 64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

Integrated Device Technology 

IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™

64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

OUTPUTS:

FULL FLAG (FF)

The Full Flag (FF) will go LOW, inhibiting further write operation, when the

device is full. If no reads are performed after Reset (RS), the Full Flag (FF)

will go LOW after 64 writes for the IDT72421, 256 writes for the IDT72201, 512

writes for the IDT72211, 1,024 writes for the IDT72221, 2,048 writes for the

IDT72231, 4,096 writes for the IDT72241, and 8,192 writes for the IDT72251.

The Full Flag (FF) is synchronized with respect to the LOW-to-HIGH

transition of the Write Clock (WCLK).

EMPTY FLAG (EF)

The Empty Flag (EF) will go LOW, inhibiting further read operations, when

the read pointer is equal to the write pointer, indicating the device is empty.

The Empty Flag (EF) is synchronized with respect to the LOW-to-HIGH

transition of the Read Clock (RCLK).

PROGRAMMABLE ALMOST-FULL FLAG (PAF)

The Programmable Almost-Full flag (PAF) will go LOW when the FIFO

reaches the almost-full condition. If no reads are performed after Reset (RS),

the Programmable Almost-Full flag (PAF) will go LOW after (64-m) writes for the

IDT72421, (256-m) writes for the IDT72201, (512-m) writes for the IDT72211,

(1,024-m) writes for the IDT72221, (2,048-m) writes for the IDT72231, (4,096-

m) writes for the IDT72241, and (8,192-m) writes for the IDT72251. The offset

“m” is defined in the Full offset registers.

If there is no Full offset specified, the Programmable Almost-Full flag (PAF)

will go LOW at Full-7 words.

The Programmable Almost-Full flag (PAF) is synchronized with respect to

the LOW-to-HIGH transition of the Write Clock (WCLK).

PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)

The Programmable Almost-Empty flag (PAE) will go LOW when the read

pointer is "n+1" locations less than the write pointer. The offset "n" is defined

in the Empty Offset registers. If no reads are performed after Reset the

Programmable Almost-Empty flag (PAE) will go HIGH after "n+1" for the

IDT72421/72201/72211/72221/72231/72241/72251.

If there is no Empty offset specified, the Programmable Almost-Empty flag

(PAE) will go LOW at Empty+7 words.

The Programmable Almost-Empty flag (PAE) is synchronized with respect

to the LOW-to-HIGH transition of the Read Clock (RCLK).

DATA OUTPUTS (Q0 - Q8)

Data outputs for a 9-bit wide data.

TABLE 1 — STATUS FLAGS

IDT72421

0

1 to n (1)

(n+1) to (64-(m+1))

(64-m)(2) to 63

64

NUMBER OF WORDS IN FIFO

IDT72201

0

1 to n (1)

(n+1) to (256-(m+1))

(256-m)(2) to 255

256

IDT72211

0

1 to n (1)

(n+1) to (512-(m+1))

(512-m)(2) to 511

512

FF PAF PAE EF

H

H

L

L

H

H

L

H

H

H

H

H

H

L

H

H

L

L

H

H

NUMBER OF WORDS IN FIFO

IDT72221

IDT72231

IDT72241

0

0

0

1 to n(1)

1 to n(1)

1 to n(1)

(n+1) to (1,024-(m+1))

(n+1) to (2,048-(m+1))

(n+1) to (4,096-(m+1))

(1,024-m)(2) to 1,023

(2,048-m)(2) to 2,047

(4,096-m)(2) to 4,095

1,024

NOTES:

1. n = Empty Offset (n = 7 default value)

2. m = Full Offset (m = 7 default value)

2,048

4,096

©

7

IDT72251

0

1 to n(1)

(n+1) to (8,192-(m+1))

(8,192-m)(2) to 8,191

8,192

FF PAF PAE EF

H

H

L

L

H

H

L

H

H

H

H

H

H

L

H

H

L

L

H

H

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