A42L0616V-60L 查看數據表（PDF） - AMIC Technology

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A42L0616V-60L

1M X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE

AMIC Technology 

A42L0616 Series

Truth Table

Function

Standby

Read: Word

Read: Lower Byte

RAS UCAS LCAS WE

OE

H

X

X

X

X

L

L

L

H

L

L

H

L

H

L

Read: Upper Byte

L

L

H

H

L

Write: Word

Write: Lower Byte

L

L

L

L

H

L

H

L

L

H

Write: Upper Byte

L

L

H

L

H

Read-Write

L

L

L

H→L L→H

EDO-Page-Mode Read: Hi-Z

-First cycle

L

H→L H→L

H

H→L

-Subsequent Cycles

L

H→L H→L

H

H→L

EDO-Page-Mode Write

-First cycle

L

H→L H→L

L

H

-Subsequent Cycles

L

H→L H→L

L

H

EDO-Page-Mode Read-Write

-First cycle

L

H→L H→L H→L L→H

-Subsequent Cycles

L

H→L H→L H→L L→H

Hidden Refresh Read

L→H→L L

L

H

L

Hidden Refresh Write

L→H→L L

L

L

X

RAS-Only Refresh

L

H

H

X

X

CBR Refresh

H→L

L

L

X

X

Self Refresh

H→L

L

L

H

X

Note: 1. Byte Write may be executed with either UCAS or LCAS active.

2. Byte Read may be executed with either UCAS or LCAS active.

3. Only one CAS signal ( UCAS or LCAS ) must be active.

Address

X

Row/Col.

Row/Col.

Row/Col.

Row/Col.

Row/Col.

Row/Col.

Row/Col.

I/Os

Notes

High-Z

Data Out

I/O0-7 = Data Out

I/O8-15 = High-Z

I/O0-7 = High-Z

I/O8-15 = Data Out

Data In

I/O0-7 = Data In

I/O8-15 = X

I/O0-7 = X

I/O8-15 = Data In

Data Out → Data In 1,2

Row/Col.

Data Out

2

Col.

Data Out

2

Row/Col.

Data In

1

Col.

Data In

1

Row/Col. Data Out → Data In 1, 2

Col.

Data Out → Data In 1, 2

Row/Col.

Data Out

2

Row/Col. Data In → High-Z 1

Row

High-Z

X

High-Z

3

X

High-Z

PRELIMINARY (June, 2001, Version 0.0)

4

AMIC Technology, Inc.

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