IDT7037L(2015) 查看數據表（PDF） - Integrated Device Technology

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IDT7037L
(Rev.:2015)

HIGH-SPEED 32K x 18 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT7037L

High-Speed 32K x 18 Dual-Port Static RAM

AC Test Conditions

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

GND to 3.0V

3ns Max.

1.5V

1.5V

Figures 1 and 2

4838 tbl 11

Industrial and Commercial Temperature Ranges

5V

5V

DATAOUT

BUSY

INT

347Ω

893Ω

DATAOUT

30pF

347Ω

893Ω

5pF*

4838 drw 03

Figure 1. AC Output Test Load

.

4838 drw 04

Figure 2. Output Test Load

(for tLZ, tHZ, tWZ, tOW)

* Including scope and jig.

Waveform of Read Cycles(5)

ADDR

CE(6)

tRC

tAA (4)

tACE (4)

tAOE (4)

OE

UB, LB

tABE (4)

R/W

DATAOUT

BUSYOUT

tLZ (1)

(4)

VALID DATA

tBDD (3,4)

tOH

tHZ (2)

4838 drw 05

Timing of Power-Up Power-Down

CE(6)

tPU

ICC

50%

tPD

50%

ISB

NOTES:

4838 drw 06 .

1. Timing depends on which signal is asserted last, OE, CE, LB or UB.

2. Timing depends on which signal is de-asserted first CE, OE, LB or UB.

3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY

has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.

5. SEM = VIH.

6. Refer to Chip Enable Truth Table.

6

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