ICS85222AM-01LF 查看數據表（PDF） - Integrated Circuit Systems

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ICS85222AM-01LF

DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL HSTL TRANSLATOR

Integrated Circuit Systems 

Integrated

Circuit

Systems, Inc.

ICS85222-01

DUAL LVCMOS / LVTTL-TO-

DIFFERENTIAL HSTL TRANSLATOR

TABLE 4A. AC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

fMAX

tPD

tsk(pp)

Output Frequency

Propagation Delay; NOTE 1

Part-to-Part Skew; NOTE 2, 3

350

MHz

700

1075

ps

375

ps

tR / tF

Output Rise/Fall Time

20% to 80%

150

ƒ ≤ 150MHz

48

800

ps

52

%

odc

Output Duty Cycle

150 < ƒ ≤ 250MHz

46

54

%

250 < ƒ ≤ 350MHz

45

55

%

NOTE 1: Measured from VDD/2 of the input to the differential output crossing point.

NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load

conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

TABLE

4B.

AC

CHARACTERISTICS,

V

DD

=

2.5V±5%,

TA

=

0°C

TO

70°C

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

fMAX

tPD

tsk(pp)

Output Frequency

Propagation Delay; NOTE 1

Part-to-Part Skew; NOTE 2, 3

350

MHz

700

1200

ps

475

ps

tR / tF

odc

Output Rise/Fall Time

Output Duty Cycle

20% to 80%

150

ƒ ≤ 150MHz

48

150 < ƒ ≤ 350MHz

46

800

ps

52

%

54

%

NOTE 1: Measured from VDD/2 of the input to the differential output crossing point.

NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load

conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

85222AM-01

www.icst.com/products/hiperclocks.html

4

REV. A NOVEMBER 15, 2005

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