810001DK-21LF 查看數據表（PDF） - Integrated Device Technology

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810001DK-21LF

FemtoClock™ Dual VCXO Video PLL

Integrated Device Technology 

ICS810001-21 Data Sheet

Applications Information

Recommendations for Unused Input Pins

Inputs:

CLK Inputs

For applications not requiring the use of a clock input, it can be left

floating. Though not required, but for additional protection, a 1kΩ

resistor can be tied from the CLK input to ground.

LVCMOS Control Pins

All control pins have internal pullups or pulldowns; additional

resistance is not required but can be added for additional protection.

A 1kΩ resistor can be used.

FEMTOCLOCK™ DUAL VCXO VIDEO PLL

Power Supply Filtering Technique

As in any high speed analog circuitry, the power supply pins are

vulnerable to random noise. To achieve optimum jitter perform ance,

power supply isolation is required. The ICS810001-21 provides

separate power supplies to isolate any high switching noise from the

outputs to the internal PLL. VDD, VDDA, VDDO and VDDX should be

individually connected to the power supply plane through vias, and

0.01µF bypass capacitors should be used for each pin. Figure 1

illustrates this for a generic VDD pin and also shows that VDDA

requires that an additional 10Ω resistor along with a 10µF bypass

capacitor be connected to the VDDA pin.

VDD

VDDX

3.3V

.01µF

10Ω

10Ω

.01µF 10µF

VDDA

.01µF 10µF

Figure 1. Power Supply Filtering

ICS810001DK-21 REVISION B APRIL 13, 2010

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©2010 Integrated Device Technology, Inc.

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