ICS527-02 查看數據表（PDF） - Integrated Circuit Systems
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ICS527-02 Datasheet PDF : 8 Pages
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ICS527-02
Clock Slicer User Configurable PECL Input Zero Delay Buffer
Multiple Output Example
In this example, an input clock of 125 MHz is used. Eight copies of 50 MHz are required as are eight copies
of 25 MHz, de-skewed and aligned to the 125 MHz input clock. The following solution uses the
MK74CB217 which has dual 1 to 8 buffers with low pin-to-pin skew.
VDD
0.01µF
125 MHz
125 MHz
R5
R6
DIV2
S0
S1
VDD
PECLIN
PECLIN
GND
OECLK2
F0
F1
F2
F3
R4
R3
R2
R1
R0
VDD
CLK1
CLK2
GND
PDTS
FBIN
F6
F5
F4
0.01µF
50M
25M
0.01µF
INA
QA0
QA1
QA2
VDD
VDD
QA3
QA4
GND
GND
QA5
QA6
QA7
OEA
INB
QB0
QB1
QB2
VDD
VDD
QB3
QB4
GND
GND
QB5
QB6
QB7
OEB
0.01µF
The layout design above produces the waveforms shown below. Note: Series terminating resistors are not shown.
125 MHz,
PECLIN
25 MHz,
QA0-7
50 MHz,
QB0-7
PECLIN not shown
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No via’s should be used
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible,
as should the PCB trace to the ground via.
2) To minimize EMI the 33Ω series termination resistor,
if needed, should be placed close to the clock outputs.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the ICS527-02. This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
MDS 527-02 F
5
Revision 022806
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
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