HYB18T1G802AF-3 查看數據表（PDF） - Infineon Technologies

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HYB18T1G802AF-3

DDR2 Registered Memory Modules

Infineon Technologies 

HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A

Registered DDR2 SDRAM Modules

3.0 Absolute Maximum Ratings

Parameter

Symbol

Limit Values

Unit

min.

max.

Voltage on any pins relative to VSS

VIN, VOUT

– 0.5

2.3

V

Voltage on VDD relative to VSS

VDD

– 1.0

2.3

V

Voltage on VDD Q relative to VSS

Storage temperature range

VDDQ

TSTG

– 0.5

-55

2.3

+100 oC

Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-

ability.

3.1 Operating Temperature Range

Parameter

DIMM Module Operating Temperature Range (ambient)

DRAM Component Case Temperature Range

Symbol

TOPR

TCASE

Limit Values

min.

max.

0

+55

0

+95

Unit Notes

oC

oC 1 - 4

1. DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs. For

measurement conditions, please refer to the JEDEC document JESD51-2.

2. Within the DRAM Component Case Temperature range all DRAM specification will be supported.

3. Above 85oC DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs.

4. Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below

85oC case temperature before initiating self-refresh operation.

3.2 Supply Voltage Levels and DC Operating Conditions

Parameter

Symbol

Limit Values

Unit Notes

min.

nom.

max.

Device Supply Voltage

VDD

1.7

1.8

1.9

V-

Output Supply Voltage

VDDQ

1.7

1.8

1.9

V 1)

Input Reference Voltage

VREF

0.49 x VDDQ

0.5 x VDDQ

0.51 x VDDQ

V 2)

EEPROM Supply Voltage

VDDSPD

1.7

–

3.6

V

DC Input Logic High

VIH (DC)

VREF + 0.125

–

VDDQ + 0.3

V

DC Input Logic Low

VIL (DC)

– 0.30

–

VREF – 0.125

V

In / Output Leakage Current IL

–5

–

5

µA 3)

1 Under all conditions, VDDQ must be less than or equal to VDD

2 Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise variations in VDDQ.

3 For any pin on the DIMM connector under test input of 0 V ≤ VIN ≤ VDDQ + 0.3 V.

Data Sheet

Preliminary

12

Rev. 0.85, 2004-04

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