HYB3117805BSJ-50 查看數據表（PDF） - Siemens AG

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HYB3117805BSJ-50

2M × 8-Bit Dynamic RAM 2k Refresh (Hyper Page Mode-EDO)

Siemens AG 

HYB 5(3)117805/BSJ-50/-60

2M × 8 EDO-DRAM

I/O1 I/O2

I/O8

WE

&

CAS

No.2 Clock

Generator

10

Column

Address

A0

Buffers (10)

A1

A2

Refresh

A3

Controller

A4

A5

A6

Refresh

A7

Counter (11)

A8

A9

11

A10

11

Row

Address

Buffers (11)

RAS

No.1 Clock

Generator

Block Diagram

Data IN

Buffer

8

Data OUT

Buffer

OE

8

10

Column

Decoder

Sense Amplifier

4

I/O Gating

1024

x8

11

Row

Decoder

2048

Memory Array

2048 x 1024 x 8

Voltage Down

Generator

SPB03456

VCC

VCC

(internal)

Semiconductor Group

3

1998-10-01

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