HM64YLB36512 查看數據表（PDF） - Renesas Electronics

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HM64YLB36512

16M Synchronous Late Write Fast Static RAM (512-kword × 36-bit)

Renesas Electronics 

HM64YLB36512 Series

Block Diagram (Register-Latch Mode)

SA0 to SA18

Read

add. reg.

Write

add. reg.

SA0 to SA18

compare

1

Memory array

(way0)

0

512k × 36

Match0

01

59-N

(x: a to d)

SWEx

1st reg.

55

SS

reg.

59-

SWE

reg.

K

/

ZQ

SWEx

2nd reg.

Byte write

control

Output

latch

Output enable

Impedance

control

Din

reg.

DQxn

(x: a to d,

n: 0 to 8)

Rev.3.00 Jan 13, 2006 page 4 of 29

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