HIP6007CB 查看數據表（PDF） - Intersil
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HIP6007CB Datasheet PDF : 10 Pages
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HIP6007
Feedback Compensation
Figure 7 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(Vout) is regulated to the Reference voltage level. The error
amplifier (Error Amp) output (VE/A) is compared with the
oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of Vin at the
PHASE node. The PWM wave is smoothed by the output
filter (Lo and Co).
OSC
VIN
DRIVER
PWM
COMPARATOR
LO
∆VOSC
-
+
DRIVER
ZFB
VE/A
-
+
ZIN
ERROR REFERENCE
AMP
PHASE
CO
ESR
(PARASITIC)
VOUT
DETAILED COMPENSATION COMPONENTS
C2
C1 R2
ZFB
VOUT
ZIN
C3 R3
R1
COMP
FB
-
+
HIP6007
REF
FIGURE 7. VOLTAGE - MODE BUCK CONVERTER
COMPENSATION DESIGN
The modulator transfer function is the small-signal transfer
function of Vout/VE/A. This function is dominated by a DC
Gain and the output filter (Lo and Co), with a double pole
break frequency at FLC and a zero at FESR. The DC Gain of
the modulator is simply the input voltage (Vin) divided by the
peak-to-peak oscillator voltage ∆VOSC.
Modulator Break Frequency Equations
FLC
=
------------------1--------------------
2π • LO • CO
FESR = 2----π-----•----(---E----S-1---R------•----C-----O----)-
The compensation network consists of the error amplifier
(internal to the HIP6007) and the impedance networks ZIN
and ZFB. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f0dB) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f0dB and
180o. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 8. Use these guidelines for
locating the poles and zeros of the compensation network:
Compensation Break Frequency Equations
FZ1 = 2----π-----•----R---1--2-----•----C----1--
FZ2 = 2----π-----•----(---R----1-----+-1----R-----3----)---•----C-----3-
FP1
=
--------------------------1---------------------------
2π • R2 • C-C----11-----+•-----CC----22--
FP2 = -2---π-----•----R---1--3-----•----C----3--
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1ST Zero Below Filter’s Double Pole
(~75% FLC)
3. Place 2ND Zero at Filter’s Double Pole
4. Place 1ST Pole at the ESR Zero
5. Place 2ND Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
Figure 8 shows an asymptotic plot of the DC-DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak do to the high Q factor of the output filter and is not
shown in Figure 8. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at FP2 with the capabilities of
the error amplifier. The Closed Loop Gain is constructed on
the log-log graph of Figure 8 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
The compensation gain uses external impedance networks
ZFB and ZIN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45o.
Include worst case component variations when determining
phase margin.
100
FZ1 FZ2 FP1 FP2
80
OPEN LOOP
60
ERROR AMP GAIN
40
20LOG
20 (R2/R1)
0
20LOG
(VIN/∆VOSC)
-20
MODULATOR
GAIN
-40
-60
FLC
FESR
10
100
1K 10K 100K
COMPENSATION
GAIN
CLOSED LOOP
GAIN
1M 10M
FREQUENCY (Hz)
FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
2-137
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