Philips Semiconductors
Programmable 4-bit binary down counter
Product specification
HEF4526B
MSI
Fig.2 Pinning diagram.
PINNING
PL
P0 to P3
CF
CP0
CP1
MR
TC
O0 to O3
parallel load input
parallel inputs
cascade feedback input
clock input (LOW to HIGH, triggered)
clock input (HIGH to LOW, triggered)
asynchronous master reset input
terminal count output
buffered parallel outputs
COUNTING MODE
CF = HIGH; PL = LOW; MR = LOW
OUTPUTS
COUNT
O3
O2
O1
O0
15
H
H
H
H
14
H
H
H
L
13
H
H
L
H
12
H
H
L
L
11
H
L
H
H
10
H
L
H
L
9
H
L
L
H
8
H
L
L
L
7
L
H
H
H
6
L
H
H
L
5
L
H
L
H
4
L
H
L
L
3
L
L
H
H
2
L
L
H
L
1
L
L
L
H
0
L
L
L
L
HEF4526BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4526BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4526BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
FUNCTION TABLE
MR PL CP0 CP1
MODE
H
X
X
X reset (asynchronous)
L
H
X
L
L
X preset (asynchronous)
H no change
L
L
L
no change
L
L
X no change
L
L
X
no change
L
L
L counter advances
L
L
H
counter advances
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
= positive-going transition
= negative-going transition
January 1995
3