Philips Semiconductors
Quadruple bilateral switches
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Power dissipation per switch
For other RATINGS see Family Specifications
DC CHARACTERISTICS
Tamb = 25 °C
VDD
V
5
ON resistance
10
15
5
ON resistance
10
15
5
ON resistance
10
15
‘∆’ ON resistance
5
between any two
10
channels
15
OFF state leakage
5
current, any
10
channel OFF
15
En input voltage
5
LOW
10
15
SYMBOL MIN. TYP. MAX.
−
350 2500 Ω
RON
−
80 245 Ω
−
60 175 Ω
−
115 340 Ω
RON
−
50 160 Ω
−
40 115 Ω
−
120 365 Ω
RON
−
65 200 Ω
−
50 155 Ω
−
25 − Ω
∆RON
−
10 − Ω
−
5−Ω
−
−
− nA
IOZ
−
−
− nA
−
−
200 nA
−
2,25
1V
VIL
−
4,50
2V
−
6,75
2V
Product specification
HEF4066B
gates
P max. 100 mW
CONDITIONS
En at VDD
Vis = VSS to VDD
see Fig.4
En at VDD
Vis = VSS
see Fig.4
En at VDD
Vis = VDD
see Fig.4
En at VDD
Vis = VSS to VDD
see Fig.4
En at VSS
Iis = 10 µA
see Fig.9
Quiescent device
current
Input leakage current at En
VDD
SYMBOL
Tamb (°c)
V
−40 +25 +85
MAX. MAX. MAX.
5
10
IDD
15
15
± IIN
1,0
1,0 7,5 µA
2,0
2,0 15,0 µA
4,0
4,0 30,0 µA
−
300 1000 nA
CONDITIONS
VSS = 0; all valid
input combinations;
VI = VSS or VDD
En at VSS or VDD
January 1995
3