HD74LV164A
Function Table
Inputs
Outputs
CLR
CLK
A
B
QA
QB
...
QD
L
X
X
X
L
L
...
L
H
H
H
H
Note:
↓
X
X
Q
Q
...
Q
A0
B0
H0
↑
H
H
H
Q
...
Q
An
Gn
↑
L
X
L
QAn
...
QGn
↑
X
L
L
QAn
...
QGn
H: High level
L: Low level
X: Immaterial
↑: Low to high transition
↓: High to low transition
QAD, QB0...QH0:
QAn, QBn...QGn:
Outputs remain unchanged.
Data shifted from the previous stage on a positive edge at the clock input.
Pin Arrangement
A1
B2
QA 3
QB 4
QC 5
QD 6
GND 7
14 VCC
13 QH
12 QG
11 QF
10 QE
9 CLR
8 CLK
(Top view)
Rev.1, Aug. 2001, page 2 of 16