HCF40105(2002) 查看數據表（PDF） - STMicroelectronics

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HCF40105
(Rev.:2002)

FIFO REGISTER

STMicroelectronics 

HCF40105B

INPUT EQUIVALENT CIRCUIT

FUNCTIONAL DIAGRAM

PIN DESCRIPTION

PIN No

1

2

3

15

14

4, 5, 6, 7

13, 12, 11,

10

9

8

16

SYMBOL NAME AND FUNCTION

3-STATE

CONTROL

3-State Control

DIR

Data-In Ready

SI

SO

DOR

D0 to D3

Shift In

Shift Out

Data-Out Ready

Input Buffers

Q0 to Q3 Output Buffers

MR

VSS

VDD

Master Reset

Negative Supply Voltage

Positive Supply Voltage

TRUTH TABLE

CLR

CONTROL INPUTS

APE

SPE

CI/CE

PRESET MODE

H

H

H

H

H

H

H

L

Synchronous

H

H

L

X

H

L

X

X

Asynchronous

L

X

X

X

X : Don’t Care

Clock connected to Clock input

Synchronous Operation : changes occur on negative to positive clock transitions.

ACTION

Inhibit Counter

Count Down

Preset on Next Positive Clock Transition

Preset Asynchronously

Clear to Maximum Count

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