H8S/2365 查看數據表（PDF） - Renesas Electronics

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H8S/2365

16-Bit Single-Chip Microcomputer

Renesas Electronics 

5.3.3 IRQ Enable Register (IER) .................................................................................. 95

5.3.4 IRQ Sense Control Register L (ISCRL)............................................................... 96

5.3.5 IRQ Status Register (ISR).................................................................................... 99

5.3.6 IRQ Pin Select Register (ITSR) ........................................................................... 100

5.3.7 Software Standby Release IRQ Enable Register (SSIER) ................................... 101

5.4 Interrupt Sources ............................................................................................................... 101

5.4.1 External Interrupts................................................................................................ 101

5.4.2 Internal Interrupts................................................................................................. 102

5.6 Interrupt Control Modes and Interrupt Operation ............................................................. 108

5.6.1 Interrupt Control Mode 0 ..................................................................................... 108

5.6.2 Interrupt Control Mode 2 ..................................................................................... 110

5.6.3 Interrupt Exception Handling Sequence .............................................................. 112

5.6.4 Interrupt Response Times .................................................................................... 114

5.6.5 DTC and DMAC Activation by Interrupt ............................................................ 115

5.7 Usage Notes ...................................................................................................................... 116

5.7.1 Contention between Interrupt Generation and Disabling..................................... 116

5.7.2 Instructions that Disable Interrupts ...................................................................... 117

5.7.3 Times when Interrupts are Disabled .................................................................... 117

5.7.4 Interrupts during Execution of EEPMOV Instruction.......................................... 117

5.7.5 Change of IRQ Pin Select Register (ITSR) Setting ............................................. 117

5.7.6 Note on IRQ Status Register (ISR) ...................................................................... 118

Section 6 Bus Controller (BSC) ...................................................................................... 119

6.1 Features ............................................................................................................................. 119

6.2 Input/Output Pins .............................................................................................................. 121

6.3 Register Descriptions ........................................................................................................ 122

6.3.1 Bus Width Control Register (ABWCR)............................................................... 123

6.3.2 Access State Control Register (ASTCR) .............................................................123

6.3.3 Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL,

WTCRBH, and WTCRBL).................................................................................. 124

6.3.4 Read Strobe Timing Control Register (RDNCR)................................................. 129

6.3.5 CS Assertion Period Control Registers H, L (CSACRH, CSACRL)................... 130

6.3.6 Area 0 Burst ROM Interface Control Register (BROMCRH) Area 1

Burst ROM Interface Control Register (BROMCRL) ......................................... 132

6.3.7 Bus Control Register (BCR) ................................................................................ 133

6.3.8 DRAM Control Register (DRAMCR) ................................................................. 135

6.3.9 DRAM Access Control Register (DRACCR) ...................................................... 140

6.3.10 Refresh Control Register (REFCR) ..................................................................... 141

6.3.11 Refresh Timer Counter (RTCNT)........................................................................ 144

6.3.12 Refresh Time Constant Register (RTCOR) ......................................................... 144

Rev. 5.00 Aug 02, 2006 page xix of liv

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