GS816018BGT-200IV 查看數據表（PDF） - Giga Semiconductor

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GS816018BGT-200IV

1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs

Giga Semiconductor 

Simplified State Diagram

Preliminary

GS8160xxBT-xxxV

X

Deselect

W

R

W

R

X

First Write R

CW

CR

First Read

X

CR

W

R

X Burst Write

CR

CW

R

Burst Read

X

CR

Notes:

1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.

2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (BA, BB, BC, BD, BW, and GW)

control inputs, and that ADSP is tied high and ADSC is tied low.

3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and

assumes ADSP is tied high and ADV is tied low.

Rev: 1.01 5/2006

10/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 2004, GSI Technology

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