SY100S336JC 查看數據表（PDF） - Micrel

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产品描述 (功能)

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SY100S336JC

4-STAGE COUNTER/SHIFT REGISTER

Micrel 

Micrel, Inc.

TIMING DIAGRAMS

0.7 ± 0.1 ns

INPUT

OUTPUT

tPHL

tTLH

0.7 ± 0.1 ns

80%

50%

20%

tPLH

–0.95V

–1.69V

80%

50%

20%

tTHL

Propagation Delay (Serial Data, Selects)

CEP

tS

D3, Pn, Sn

tS

CLOCK

INHIBIT COUNT

50%

ENABLE COUNT

tH

50%

tH

50%

–0.95V

–1.69V

–0.95V

–1.69V

–0.95V

–1.69V

Set-up and Hold Time

Notes:

1. VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND.

2. tS is the minimum time before the transition of the clock that information must be present at the data input.

3. tH is the minimum time after the transition of the clock that information must remain unchanged at the data input.

SY100S336

M9999-032206

hbwhelp@micrel.com or (408) 955-1690

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