SY100S336(1999) 查看數據表（PDF） - Micrel

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SY100S336
(Rev.:1999)

4-STAGE COUNTER/SHIFT REGISTER

Micrel 

Micrel

TIMING DIAGRAMS

0.7 ± 0.1 ns

INPUT

OUTPUT

tPHL

tTLH

0.7 ± 0.1 ns

80%

50%

20%

tPLH

–0.95V

–1.69V

80%

50%

20%

tTHL

Propagation Delay (Serial Data, Selects)

CEP

tS

D3, Pn, Sn

tS

CLOCK

INHIBIT COUNT

50%

ENABLE COUNT

tH

50%

tH

50%

–0.95V

–1.69V

–0.95V

–1.69V

–0.95V

–1.69V

Set-up and Hold Time

NOTES:

1. VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND.

2. tS is the minimum time before the transition of the clock that information must be present at the data input.

3. tH is the minimum time after the transition of the clock that information must remain unchanged at the data input.

PRODUCT ORDERING CODE

Ordering

Code

SY100S336FC

SY100S336JC

SY100S336JCTR

Package

Type

F24-1

J28-1

J28-1

Operating

Range

Commercial

Commercial

Commercial

7

SY100S336

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