FS6131-01G-XTD 查看數據表（PDF） - ON Semiconductor

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FS6131-01G-XTD

Programmable Line Lock Clock Generator IC

ON Semiconductor 

FS6131

The transfer function of the feedback divider is:

KF

=

1

NF

Finally, the sampling effect that occurs in the phase detector is accounted for by:

K SAMP

( s)

=

⎜⎛1 −

⎜

⎜⎝

e −⎜⎝⎛ s

s

f REF

⎟⎠⎞

⎟⎞

⎟

⎟⎠

f REF

The loop gain of the PLL is:

K LOOP (s) = K PD K LF (s)KVCO (s)K F K SAMP (s)

100

10

1

The loop phase angle is:

0.1

0.01

0.1kHz

1kHz

10kHz

Frequency (fi)

Figure 8: Loop Gain vs. Frequency

100kHz

[ ] Θi = arg K LOOP ( j2πfi)

Rev. 4 | Page 8 of 44 | www.onsemi.com

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