DS1045-5 查看數據表（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS1045-5

4-Bit Dual Programmable Delay Line

Dallas Semiconductor -> Maxim Integrated 

TIMING DIAGRAM: DS1045 INPUTS TO OUTPUTS

DS1045

TERMINOLOGY

PERIOD: The time elapsed between the leading edge of the first pulse and the leading edge of the

following pulse.

tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the 1.5V

point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V on the leading edge.

tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the

input pulse.

tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the

input pulse.

tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input

pulse and the 1.5V point on the leading edge of the output pulse.

tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input

pulse and the 1.5V point on the trailing edge of the output pulse.

NOTES:

1. All voltages are referenced to ground.

2. @ VCC = 5V and 25°C. Delay accurate on both rising and falling edges within tolerances given in

Table 1.

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