DSP56367UM 查看數據表（PDF） - Freescale Semiconductor

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DSP56367UM

24-Bit Audio Digital Signal Processor

Freescale Semiconductor 

External Clock Operation

Table 3-4 Internal Clocks (continued)

Characteristics

Symbol

Min

Expression1, 2

Typ

Max

Internal clock cycle time with PLL disabled

TC

—

2 × ETC

—

Instruction cycle time

ICYC

—

TC

—

1 DF = Division Factor

Ef = External frequency

ETC = External clock cycle

MF = Multiplication Factor

PDF = Predivision Factor

TC = internal clock cycle

2 Refer to the DSP56300 Family Manual for a detailed discussion of the PLL.

3.7 External Clock Operation

The DSP56367 system clock is an externally supplied square wave voltage source connected to

EXTAL(Figure 3-1).

EXTAL

VILC ETH 2

ETL

3

4

ETC

Midpoint

VIHC

Note: The midpoint is 0.5 (VIHC + VILC).

Figure 3-1 External Clock Timing

Table 3-5 Clock Operation

No.

Characteristics

Symbol

1 Frequency of EXTAL (EXTAL Pin Frequency)

Ef

The rise and fall time of this external clock should be 2 ns maximum.

2 EXTAL input high1, 2

ETH

• With PLL disabled (46.7%–53.3% duty cycle3)

• With PLL enabled (42.5%–57.5% duty cycle3)

3 EXTAL input low1, 2

ETL

• With PLL disabled (46.7%–53.3% duty cycle3)

• With PLL enabled (42.5%–57.5% duty cycle3)

Min

2.0 ns

3.11 ns

2.83 ns

3.11 ns

2.83 ns

Max

150.0

∞

157.0 µs

∞

157.0 µs

DSP56367 Technical Data, Rev. 2.1

Freescale Semiconductor

3-5

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