DS21455N 查看數據表（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS21455N

Quad T1/E1/J1 Transceivers

Dallas Semiconductor -> Maxim Integrated 

DS21455/DS21458 Quad T1/E1/J1 Transceivers

Figure 38-13. Transmit Side Timing

tR

TCLK

TESO

TSER / TSIG /

TDATA

TCHCLK

tF

t D1

t D2

tCP

tCL tCH

t SU

tHD

TCHBLK

TSYNC1

TSYNC2

TLCLK5

TLINK

t D2

t D2

t SU

t HD

t D2

tHD

t SU

NOTES:

1) TSYNC is in the output mode (TCR2.2 = 1).

2) TSYNC is in the input mode (TCR2.2 = 0).

3) TSER is sampled on the falling edge of TCLK when the transmit-side elastic store is disabled.

4) TCHCLK and TCHBLK are synchronous with TCLK when the transmit-side elastic store is disabled.

5) TLINK is only sampled during F-bit locations.

6) No relationship between TCHCLK and TCHBLK and the other signals is implied.

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