DS21455N 查看數據表（PDF） - Dallas Semiconductor -> Maxim Integrated
零件编号
产品描述 (功能)
生产厂家
DS21455N Datasheet PDF : 270 Pages
| |||
DS21455/DS21458 Quad T1/E1/J1 Transceivers
38.4 Transmit AC Characteristics
AC CHARACTERISTICS–TRANSMIT SIDE
(VDD = 3.3V ±5%, TA = 0°C to +70°C for DS21455/DS21458;
VDD = 3.3V ±5%, TA = -40°C to +85°C; for DS21455N/DS21458N.) (See Figure 38-13 to Figure 38-15.)
PARAMETER
SYMBOL MIN TYP (E1) MAX UNITS NOTES
TCLK Period
tCP
488 (E1)
ns
648 (T1)
TCLK Pulse Width
tCH
20
0.5 tCP
ns
tCL
20
0.5 tCP
ns
TCLKI Period
tLP
488 (E1)
ns
648 (T1)
TCLKI Pulse Width
tLH
20
0.5 tLP
ns
tLL
20
0.5 tLP
ns
648
ns
1
448
ns
2
TSYSCLK Period
tSP
244
ns
3
122
ns
4
TSYSCLK Pulse Width
tSP
TSYNC or TSSYNC Setup to TCLK
or TSYSCLK Falling
tSU
61
20
0.5 tSP
20
0.5 tSP
20
ns
5
ns
ns
ns
TSYNC or TSSYNC Pulse Width
tPW
50
TSER, TSIG, TDATA, TLINK,
TPOSI, TNEGI Setup to TCLK,
tSU
20
TSYSCLK, TCLKI Falling
TSER, TSIG, TDATA, TLINK Hold
from TCLK or TSYSCLK, Falling
tHD
20
TPOSI, TNEGI Hold from TCLKI
Falling
tHD
20
TCLK, TCLKI, or TSYSCLK Rise
and Fall Times
tR, tF
Delay TCLKO to TPOSO, TNEGO
Valid
tDD
ns
ns
ns
ns
25
ns
50
ns
Delay TCLK to TESO Valid
tD1
50
ns
Delay TCLK to TCHBLK, TCHCLK,
TSYNC, TLCLK
tD2
Delay TSYSCLK to TCHCLK,
TCHBLK
tD3
50
ns
22
ns
NOTES:
1) TSYSCLK = 1.544MHz.
2) TSYSCLK = 2.048MHz.
3) TSYSCLK = 4.096MHz.
4) TSYSCLK = 8.192MHz.
5) TSYSCLK = 16.384MHz.
265 of 270
Share Link: 