DS21455N 查看數據表（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS21455N

Quad T1/E1/J1 Transceivers

Dallas Semiconductor -> Maxim Integrated 

DS21455/DS21458 Quad T1/E1/J1 Transceivers

Figure 38-9. Receive Side Timing, Elastic Store Disabled (E1 Mode)

RCLK

t D1

RSER / RDATA / RSIG

t D2

MSB of

Channel 1

RCHCLK

t D2

RCHBLK

t D2

RFSYNC / RMSYNC

RSYNC1

RLCLK2

RLINK

t D2

tD2

t D1

Sa4 to Sa8

Bit Position

Notes:

1. RSYNC is in the output mode (RCR1.5 = 0).

2. RLCLK will only pulse high during Sa bit locations as defined in RCR2; no relationship

between RLCLK and RSYNC or RFSYNC is implied.

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