DS1258W-150-IND(2002) 查看數據表（PDF） - Dallas Semiconductor -> Maxim Integrated
零件编号
产品描述 (功能)
生产厂家
DS1258W-150-IND Datasheet PDF : 9 Pages
| |||
DS1258W
READ MODE
The DS1258W executes a read cycle whenever WE (Write Enable) is inactive (high) and either/both of
CEU or CEL (Chip Enables) are active (low) and OE (Output Enable)is active (low). The unique address
specified by the 17 address inputs (A0-A16) defines which of the 131,072 words of data is accessed. The
status of CEU and CEL determines whether all or part of the addressed word is accessed. If CEU is active
with CEL inactive, then only the upper byte of the addressed word is accessed. If CEU is inactive with
CEL active, then only the lower byte of the addressed word is accessed. If both the CEU and CEL inputs
are active (low), then the entire 16-bit word is accessed. Valid data will be available to the 16 data output
drivers within tACC (Access Time) after the last address input signal is stable, providing that CEU , CEL
and OE access times are also satisfied. If CEU , CEL , and OE access times are not satisfied, then data
access must be measured from the later-occurring signal, and the limiting parameter is either tCO for CEU ,
CEL , or tOE for OE rather than address access.
WRITE MODE
The DS1258W executes a write cycle whenever WE and either/both of CEU or CEL are active (low)
after address inputs are stable. The unique address specified by the 17 address inputs (A0-A16) defines
which of the 131,072 words of data is accessed. The status of CEU and CEL determines whether all or
part of the addressed word is accessed. If CEU is active with CEL inactive, then only the upper byte of
the addressed word is accessed. If CEU is inactive with CEL active, then only the lower byte of the
addressed word is accessed. If both the CEU and CEL inputs are active (low), then the entire 16-bit word
is accessed. The write cycle is terminated by the earlier rising edge of CEU and/or CEL , or WE . All
address inputs must be kept valid throughout the write cycle. WE must return to the high state for a
minimum recovery time (tWR) before another cycle can be initiated. The OE control signal should be kept
inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled
( CEU and/or CEL , and OE active) then WE will disable the outputs in tODW from its falling edge.
READ/WRITE FUNCTION Table 1
VCC
OE
WE
CEL
CEU CURRENT
H
H
X
X
ICCO
L
H
L
L
L
H
L
H
ICCO
L
H
H
L
X
L
L
L
X
L
L
H
ICCO
X
L
H
L
X
X
H
H
ICCS
DQ0-DQ7
High-Z
Output
Output
High-Z
Input
Input
High-Z
High-Z
DQ8-DQ15
High-Z
Output
High-Z
Output
Input
High-Z
Input
High-Z
CYCLE
PERFORMED
Output Disabled
Read Cycle
Write Cycle
Output Disabled
DATA RETENTION MODE
The DS1258W provides full functional capability for VCC greater than 3.0V, and write-protects by 2.8V.
Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile static
RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically write-
protect themselves, all inputs become “don’t care,” and all outputs become high impedance. As VCC falls
below approximately 2.5V, a power-switching circuit connects the lithium energy source to RAM to
retain data. During power-up, when VCC rises above approximately 2.5V, the power switching circuit
2 of 9
Share Link: 