DS1238 查看數據表（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS1238

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Dallas Semiconductor -> Maxim Integrated 

POWER SWITCHING Figure 9

DS1238

Note: If freshness on the DS1238 is not used, PF on the DS1336 may be tied to OUT1. This will free IN4, OUT4,

and VBAT01 for system use.

TIMING DIAGRAMS

This section provides a description of the timing diagrams shown in Figure 10 and Figure 11. Figure 10

illustrates the relationship for power down. As VCC falls, the IN pin voltage drops below VTP. As a result,

the processor is notified of an impending power failure via an active NMI . This gives the processor time

to save critical data in nonvolatile SRAM. As the power falls further, VCC crosses VCCTP, the power

monitor trip point. When VCC reaches VCCTP, and active RST and RST are given. At this time, CEO is

brought high to write-protect the RAM. When the VCC reaches VBAT, a power-fail is issued via the PF pin.

Figure 11 shows the power-up sequence. As VCC slews above VBAT, the PF pin is deactivated. An active

reset occurs as well as an NMI . Although the NMI may be short due to slew rates, reset will be

maintained for the standard tRPU timeout period . At a later time, if the IN pin falls below VTP, a new NMI

will occur. If the processor does not issue an ST , a watchdog reset will also occur. The second NMI and

RST are provided to illustrate these possibilities.

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