DM74S175 查看數據表（PDF） - Fairchild Semiconductor
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DM74S175 Datasheet PDF : 5 Pages
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Function Table (Each Flip-Flop)
Inputs
Clear
Clock
D
L
X
X
H
↑
H
H
↑
L
H
L
X
H = HIGH Level (steady state)
L = LOW Level (steady state)
X = Don’t Care
↑ = Transition from LOW-to-HIGH level
Q0 = The level of Q before the indicated steady-state input conditions were established.
Note 1: DM74S175 only.
Logic Diagrams
DM74S174
Outputs
Q
Q (Note 1)
L
H
H
L
L
H
Q0
Q0
DM74S175
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