Integrated Device Technology
DAC1003D160
Dual 10 bits DAC, up to 160 MHz, 2 x interpolation
I0 to I9,
Q0 to Q9
CLKN
CLK
tsu(i)
th(i)
50 %
IOUT/IOUTN,
QOUT/QOUTN
Fig 5. Input timing diagram
014aaa534
DAC1003D160_3
Product data sheet
Rev. 03 — 2 July 2012
© IDT 2012. All rights reserved.
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