CY7C164(2006) 查看數據表（PDF） - Cypress Semiconductor
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CY7C164 Datasheet PDF : 9 Pages
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AC Test Loads and Waveforms
5V
OUTPUT
R1 481Ω
5V
OUTPUT
R1 481Ω
30 pF
INCLUDING
JIG AND
SCOPE (a)
R2
255Ω
5 pF
INCLUDING
JIG AND
SCOPE (b)
Equivalent to:
THÉVENIN EQUIVALENT
OUTPUT
167Ω
1.73V
R2
255Ω
C164–5
Switching Characteristics Over the Operating Range[4]
Parameter
Description
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Output Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low Z
tHZOE
tLZCE
tHZCE
OE HIGH to High Z
CE LOW to Low Z[5]
CE HIGH to High Z[5, 6]
tPU
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
WRITE CYCLE[7]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[5]
WE LOW to High Z[5, 6]
7C166
7C166
7C166
CY7C164
CY7C166
3.0V
10%
GND
< 5 ns
ALL INPUT PULSES
90%
90%
10%
< 5 ns
C164–6
CY7C164-15
CY7C166-15
CY7C164-25
CY7C166-25
Min.
Max.
Min.
Max.
Unit
15
25
ns
15
25
ns
3
5
ns
15
25
ns
10
12
ns
3
3
ns
8
10
ns
3
5
ns
8
10
ns
0
0
ns
15
20
ns
15
20
ns
12
20
ns
12
20
ns
0
0
ns
0
0
ns
12
15
ns
10
10
ns
0
0
ns
5
5
ns
7
7
ns
Notes:
4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device. These parameters are guaranteed by design and not 100% tested.
6. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) in AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a
write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05025 Rev. *A
Page 3 of 9
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