CY7C1355C 查看數據表（PDF） - Cypress Semiconductor

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CY7C1355C

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL™ Architecture

Cypress Semiconductor 

CY7C1355C

CY7C1357C

Switching Waveforms

Read/Write Waveforms[22, 23, 24]

1

2 tCYC 3

4

5

6

7

8

9

10

CLK

tCENS tCENH

tCH tCL

CEN

tCES tCEH

CE

ADV/LD

WE

BWX

ADDRESS A1

A2

tAS tAH

A3

tCDV

tCLZ

A4

tDOH

A5

A6

tOEV tCHZ

DQ

D(A1)

D(A2) D(A2+1)

OE

COMMAND

tDS tDH

WRITE

D(A1)

WRITE

D(A2)

BURST

WRITE

D(A2+1)

READ

Q(A3)

Q(A3) Q(A4)

Q(A4+1)

D(A5)

tOEHZ

tDOH

tOELZ

READ

Q(A4)

BURST

READ

Q(A4+1)

WRITE

D(A5)

READ

Q(A6)

A7

Q(A6)

D(A7)

WRITE

D(A7)

DESELECT

DON’T CARE

UNDEFINED

Notes:

22. For this waveform ZZ is tied LOW.

23. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

24. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.

Document #: 38-05539 Rev. *E

Page 21 of 28

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