CY7C1324H 查看數據表（PDF） - Cypress Semiconductor
零件编号
产品描述 (功能)
生产厂家
CY7C1324H Datasheet PDF : 15 Pages
| |||
CY7C1324H
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
Supply Voltage on VDDQ Relative to GND ...... –0.5V to +VDD
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to VDDQ + 0.5V
Range
Commercial
Industrial
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
VDD
3.3V
−5%/+10%
VDDQ
2.5V –5%
to VDD
Electrical Characteristics Over the Operating Range [6, 7]
Parameter
Description
Test Conditions
Min.
VDD
VDDQ
Power Supply Voltage
I/O Supply Voltage
for 3.3V I/O
for 2.5V I/O
3.135
3.135
2.375
VOH
Output HIGH Voltage for 3.3V I/O, IOH = –4.0 mA
for 2.5V I/O, IOH = –1.0 mA
VOL
Output LOW Voltage for 3.3V I/O, IOL = 8.0 mA
for 2.5V I/O, IOL = 1.0 mA
VIH
Input HIGH Voltage for 3.3V I/O
for 2.5V I/O
VIL
Input LOW Voltage[6] for 3.3V I/O
for 2.5V I/O
2.4
2.0
2.0
1.7
–0.3
–0.3
IX
Input Leakage Current GND ≤ VI ≤ VDDQ
−5
except ZZ and MODE
Input Current of MODE Input = VSS
–30
Input = VDD
Input Current of ZZ
Input = VSS
–5
Input = VDD
IOZ
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
–5
IDD
VDD Operating Supply VDD = Max., IOUT = 0 mA,
7.5-ns cycle, 133 MHz
Current
f = fMAX= 1/tCYC
ISB1
Automatic CE
Max. VDD, Device Deselected, 7.5-ns cycle, 133 MHz
Power-Down
VIN ≥ VIH or VIN ≤ VIL, f = fMAX,
Current—TTL Inputs inputs switching
ISB2
Automatic CE
Max. VDD, Device Deselected, 7.5-ns cycle, 133 MHz
Power-Down
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
Current—CMOS Inputs f = 0, inputs static
ISB3
Automatic CE
Max. VDD, Device Deselected, 7.5-ns cycle, 133 MHz
Power-Down
VIN ≥ VDDQ – 0.3V or VIN ≤
Current—CMOS Inputs 0.3V,
f = fMAX, inputs switching
ISB4
Automatic CE
Max. VDD, Device Deselected, 7.5-ns cycle, 133 MHz
Power-Down
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
Current—TTL Inputs f = 0, inputs static
Notes:
6. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).
7. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Max.
3.6
VDD
2.625
Unit
V
V
V
V
0.4
V
0.4
VDD + 0.3V V
VDD + 0.3V
0.8
V
0.7
5
µA
µA
5
µA
µA
30
µA
5
µA
225
mA
90
mA
40
mA
75
mA
45
mA
Document #: 001-00208 Rev. *B
Page 7 of 15
[+] Feedback
Share Link: 