CY14B256PA 查看數據表（PDF） - Cypress Semiconductor
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CY14B256PA Datasheet PDF : 43 Pages
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CY14C256PA
CY14B256PA
CY14E256PA
Figure 9. WREN Instruction
CS
SCK
01 234567
SI
00000110
SO
HI-Z
Write Disable (WRDI) Instruction
Write Disable instruction disables the write by clearing the WEN
bit to ‘0’ to protect the device against inadvertent writes. This
instruction is issued following the falling edge of CS followed by
opcode for WRDI instruction. The WEN bit is cleared on the
rising edge of CS following a WRDI instruction.
Figure 10. WRDI Instruction
CS
SCK
01 234567
SI
00000100
SO
HI-Z
Block Protection
Block protection is provided using the BP0 and BP1 pins of the
Status Register. These bits can be set using WRSR instruction
and probed using the RDSR instruction. The nvSRAM is divided
into four array segments. One-quarter, one-half, or all of the
memory segments can be protected. Any data within the
protected segment is read only. Table 4 shows the function of
Block Protect bits.
Table 4. Block Write Protect Bits
Level
0
1 (1/4)
2 (1/2)
3 (All)
Status Register Bits
Array Addresses Protected
BP1
BP0
0
0
None
0
1
0x6000–0x7FFF
1
0
0x4000–0x7FFF
1
1
0x0000–0x7FFF
Hardware Write Protection (WP Pin)
The write protect pin (WP) is used to provide hardware write
protection. WP pin enables all normal read and write operations
when held HIGH. When the WP pin is brought LOW and WPEN
bit is ‘1’, all write operations to the Status Register are inhibited.
The hardware write protection function is blocked when the
WPEN bit is ‘0’. This allows you to install the device in a system
with the WP pin tied to ground, and still write to the Status
Register.
WP pin can be used along with WPEN and Block Protect bits
(BP1 and BP0) of the Status Register to inhibit writes to memory.
When WP pin is LOW and WPEN is set to ‘1’, any modifications
to Status Register are disabled. Therefore, the memory is
protected by setting the BP0 and BP1 bits and the WP pin inhibits
any modification of the Status Register bits, providing hardware
write protection.
Note WP going LOW when CS is still LOW has no effect on any
of the ongoing write operations to the Status Register.
Table 5 summarizes all the protection features provided in the
CY14X256PA.
Table 5. Write Protection Operation
WPEN WP
X
X
0
X
1 LOW
1 HIGH
WEN
Protected Unprotected
Blocks
Blocks
Status
Register
0 Protected Protected Protected
1 Protected Writable Writable
1 Protected Writable Protected
1 Protected Writable Writable
Memory Access
All memory accesses are done using the READ and WRITE
instructions. These instructions cannot be used while a STORE
or RECALL cycle is in progress. A STORE cycle in progress is
indicated by the RDY bit of the Status Register and the HSB pin.
Read Sequence (READ) Instruction
The read operations on CY14X256PA are performed by giving
the instruction on the SI pin and reading the output on SO pin.
The following sequence needs to be followed for a read
operation: After the CS line is pulled LOW to select a device, the
read opcode is transmitted through the SI line followed by two
bytes of address. The MSB bit (A15) of the address is a “don’t
care”. After the last address bit is transmitted on the SI pin, the
data (D7-D0) at the specific address is shifted out on the SO line
on the falling edge of SCK starting with D7. Any other data on SI
line after the last address bit is ignored.
CY14X256PA allows reads to be performed in bursts through
SPI which can be used to read consecutive addresses without
issuing a new READ instruction. If only one byte is to be read,
the CS line must be driven HIGH after one byte of data comes
out. However, the read sequence may be continued by holding
the CS line LOW and the address is automatically incremented
and data continues to shift out on SO pin. When the last data
memory address (0x7FFF) is reached, the address rolls over to
0x0000 and the device continues to read.
Note READ instruction operates up to Max of 40 MHz SPI
frequency.
Fast Read Sequence (FAST_READ) Instruction
The FAST_READ instruction allows you to read memory at SPI
frequency above 40 MHz and up to 104 MHz (Max). The host
system must first select the device by driving CS LOW, the
FAST_READ instruction is then written to SI, followed by 2
Document Number: 001-65281 Rev. *G
Page 12 of 43
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