CY14B256PA 查看數據表（PDF） - Cypress Semiconductor
零件编号
产品描述 (功能)
生产厂家
CY14B256PA Datasheet PDF : 43 Pages
| |||
CY14C256PA
CY14B256PA
CY14E256PA
Figure 6. Read Status Register (RDSR) Instruction Timing
CS
SCK
SI
0 1 2 3 4 5 67 01 2 3 4 5 67
Op-Code
0 0 0 0 01 0 1 0
SO
HI-Z
D7 D6 D5 D4 D3 D2 D1 D0
MSB
Data
LSB
Figure 7. Fast Read Status Register (FAST_RDSR) Instruction Timing
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
Op-Code
Dummy Byte
SI
0 0 0 0 1 00 1 XXXXX XXX 0
SO
HI-Z
D7 D6 D5 D4 D3 D2 D1 D0
MSB
Data
LSB
Figure 8. Write Status Register (WRSR) Instruction Timing
CS
SCK
01 23 4 5 6 701 2 3 4 5 6 7
Opcode
Data in
SI
0 0 0 0 0 0 0 1 D7 X X X D3 D2 X X
MSB
LSB
SO
HI-Z
Write Protection and Block Protection
CY14X256PA provides features for both software and hardware
write protection using WRDI instruction and WP. Additionally, this
device also provides block protection mechanism through BP0
and BP1 pins of the Status Register.
The write enable and disable status of the device is indicated by
WEN bit of the Status Register. The write instructions (WRSR,
WRITE, WRTC and WRSN) and nvSRAM special instruction
(STORE, RECALL, ASENB, ASDISB) need the write to be
enabled (WEN bit = ‘1’) before they can be issued.
Write Enable (WREN) Instruction
On power-up, the device is always in the write disable state. The
following WRITE, WRSR, WRTC, WRSN or nvSRAM special
instruction must therefore be preceded by a Write Enable
instruction. If the device is not write enabled (WEN = ‘0’), it
ignores the write instructions and returns to the standby state
when CS is brought HIGH. A new CS falling edge is required to
re-initiate serial communication. The instruction is issued
following the falling edge of CS. When this instruction is used,
the WEN bit of Status Register is set to ‘1’. WEN bit defaults to
‘0’ on power-up.
Note After completion of a write instruction (WRSR, WRITE,
WRTC or WRSN) or nvSRAM special instruction (STORE,
RECALL, ASENB, ASDISB) instruction, WEN bit is cleared to ‘0’.
This is done to provide protection from any inadvertent writes.
Therefore, WREN instruction needs to be used before a new
write instruction is issued.
Document Number: 001-65281 Rev. *G
Page 11 of 43
Share Link: 