CY14C101I(2012) 查看數據表（PDF） - Cypress Semiconductor

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CY14C101I
(Rev.:2012)

1-Mbit (128 K × 8) Serial (I2C) nvSRAM with Real Time Clock

Cypress Semiconductor 

PRELIMINARY

CY14C101I

CY14B101I

CY14E101I

Real Time Clock Operation

nvTIME Operation

The CY14X101I offers internal registers that contain clock,

alarm, watchdog, interrupt, and control functions. The RTC

registers occupy a separate address space from nvSRAM and

are accessible through the Read RTC register and Write RTC

register sequence on register addresses 0x00 to 0x0F. Internal

double buffering of the clock and the timer information registers

prevents accessing transitional internal clock data during a read

or write operation. Double buffering also circumvents disrupting

normal timing counts or the clock accuracy of the internal clock

when accessing clock data. Clock and alarm registers store data

in BCD format.

Clock Operations

The clock registers maintain time up to 9,999 years in

one-second increments. The time can be set to any calendar

time and the clock automatically keeps track of days of the week

and month, leap years, and century transitions. There are eight

registers dedicated to the clock functions, which are used to set

time with a write cycle and to read time with a read cycle. These

registers contain the time of day in BCD format. Bits defined as

‘0’ are currently not used and are reserved for future use by

Cypress.

Reading the Clock

The double buffered RTC register structure reduces the chance

of reading incorrect data from the clock. Internal updates to the

CY14X101I time keeping registers are stopped when the read bit

‘R’ (in the flags register at 0x00) is set to ‘1’ before reading clock

data to prevent reading of data in transition. Stopping the register

updates does not affect clock accuracy.

When a read sequence of RTC device is initiated, the update of

the user timekeeping registers stops and does not restart until a

STOP or a Repeated START condition is generated. The RTC

registers are read while the internal clock continues to run. After

the end of read sequence, all the RTC registers are

simultaneously updated within 20 ms.

Setting the Clock

A write access to the RTC device stops updates to the time

keeping registers and enables the time to be set when the write

bit ‘W’ (in the flags register at 0x00) is set to ‘1’. The correct day,

date, and time is then written into the registers and must be in 24

hour BCD format. The time written is referred to as the “Base

Time”. This value is stored in nonvolatile registers and used in

the calculation of the current time. When the write bit ‘W’ is

cleared by writing ‘0’ to it and a STOP or Repeated START

condition is encountered, the values of timekeeping registers are

transferred to the actual clock counters after which the clock

resumes normal operation. If a valid STOP or Repeated START

condition is not generated by the master, the time written to the

RTC registers is never transferred to the actual clock counters.

If the time written to the timekeeping registers is not in the correct

BCD format, each invalid nibble of the RTC registers continue

counting to 0xF before rolling over to 0x0 after which RTC

resumes normal operation.

Note After ‘W’ bit is set to ‘0’, values written into the timekeeping,

alarm, calibration, and interrupt registers are transferred to the

RTC time keeping counters in tRTCp time. These counter values

must be saved to nonvolatile memory either by initiating a

Software/Hardware STORE or AutoStore operation. While

working in AutoStore disabled mode, perform a STORE

operation after tRTCp time while writing into the RTC registers for

the modifications to be correctly recorded.

Backup Power

The RTC in the CY14X101I is intended for permanently powered

operation. The VRTCcap or VRTCbat pin is connected depending

on whether a capacitor or battery is chosen for the application.

When the primary power, VCC, fails and drops below VSWITCH

the device switches to the backup power supply.

The clock oscillator uses very little current, which maximizes the

backup time available from the backup source. Regardless of the

clock operation with the primary source removed, the data stored

in the nvSRAM is secure, having been stored in the nonvolatile

elements when power was lost.

During backup operation, the CY14X101I consumes a 0.45 µA

(Typ) at room temperature. The user must choose capacitor or

battery values according to the application.

Backup time values based on maximum current specifications

are shown in the following table. Nominal backup times are

approximately two times longer.

Table 7. RTC Backup Time

Capacitor Value

0.1F

0.47F

1.0F

Backup Time

(CY14B101I)

60 hours

12 days

25 days

Using a capacitor has the obvious advantage of recharging the

backup source each time the system is powered up. If a battery

backup is used, a 3-V lithium battery is recommended and the

CY14X101I sources current only from the battery when the

primary power is removed. However, the battery is not recharged

at any time by the CY14X101I. The battery capacity must be

chosen for total anticipated cumulative down time required over

the life of the system.

Stopping and Starting the Oscillator

The OSCEN bit in the calibration register at 0x08 controls the

enable and disable of the oscillator. This bit is nonvolatile and is

shipped to customers in the “enabled” (set to ‘0’) state. To

preserve the battery life when the system is in storage, OSCEN

must be set to ‘1’. This turns off the oscillator circuit, extending

the battery life. If the OSCEN bit goes from disabled to enabled,

it takes approximately one second (two seconds maximum) for

the oscillator to start.

While system power is off, if the voltage on the backup supply

(VRTCcap or VRTCbat) falls below their respective minimum level,

the oscillator may fail.The CY14X101I has the ability to detect

oscillator failure when system power is restored. This is recorded

in the Oscillator Fail Flag (OSCF) of the flags register at the

address 0x00. When the device is powered on (VCC goes above

VSWITCH) the OSCEN bit is checked for the ‘enabled’ status. If

the OSCEN bit is enabled and the oscillator is not active within

the first 5 ms, the OSCF bit is set to ‘1’. The system must check

for this condition and then write ‘0’ to clear the flag.

Document Number: 001-54391 Rev. *G

Page 20 of 41

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