CDP1802BCQ 查看數據表（PDF） - Intersil

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CDP1802BCQ

CMOS 8-Bit Microprocessors

Intersil 

CDP1802A, CDP1802AC, CDP1802BC

Machine Cycle Timing Waveforms (Propagation Delays Not Shown) (Continued)

01234567012345670123456

CLOCK

TPA

TPB

MACHINE

CYCLE

CYCLE n

CYCLE (n + 1)

CYCLE (n + 2)

INSTRUCTION

FETCH (S0)

EXECUTE (S1)

INTERRUPT (S3)

MRD

MWR

INTERRUPT

(NOTE 1)

(INTERNAL) IE

MEMORY

OUTPUT

MEMORY READ CYCLE

NOTE 1

USER GENERATED SIGNAL

VALID OUTPUT

MEMORY READ, WRITE

OR NON-MEMORY CYCLE

“DON’T CARE” OR INTERNAL DELAYS

NON-MEMORY CYCLE

HIGH IMPEDANCE STATE

FIGURE 14. INTERRUPT CYCLE TIMING WAVEFORMS

Performance Curves

8

CL, LOAD CAPACITANCE = 50pF

7

VCC = VDD = 10V

6

5

VCC = 5V, VDD = 10V

4

3

VCC = VDD = 5V

2

1

0

25 35 45 55 65 75 85 95 105 115 125

TA, AMBIENT TEMPERATURE (oC)

FIGURE 15. CDP1802A, AC TYPICAL MAXIMUM CLOCK

FREQUENCY AS A FUNCTION OF TEMPERATURE

8

CL, LOAD CAPACITANCE = 50pF

7

6

5

VCC = VDD = 5V

4

3

2

1

0

25 35 45 55 65 75 85 95 105 115 125

TA, AMBIENT TEMPERATURE (oC)

FIGURE 16. CDP1802BC TYPICAL MAXIMUM CLOCK

FREQUENCY AS A FUNCTION OF TEMPERATURE

3-17

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