CDP1802BCE 查看數據表（PDF） - Intersil

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CDP1802BCE

CMOS 8-Bit Microprocessors

Intersil 

CDP1802A, CDP1802AC, CDP1802BC

Machine Cycle Timing Waveforms (Propagation Delays Not Shown) (Continued)

0

1

2

3

4

5

6

7

0

1

2

3

4

CLOCK

5

6

7

0

TPA

TPB

MACHINE

CYCLE

CYCLE n

CYCLE (n + 1)

INSTRUCTION

FETCH (S0)

EXECUTE (S1)

MRD

N0 - N2

N=9-F

MWR

MEMORY

OUTPUT

DATA

BUS

(NOTE 1)

ALLOWABLE MEMORY ACCESS

MEMORY READ CYCLE

VALID OUTPUT

VALID DATA FROM INPUT DEVICE

MEMORY WRITE CYCLE

NOTE 1

USER GENERATED SIGNAL

“DON’T CARE” OR INTERNAL DELAYS

HIGH IMPEDANCE STATE

FIGURE 10. INPUT CYCLE TIMING WAVEFORMS

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

CLOCK

TPA

TPB

MACHINE

CYCLE

CYCLE n

CYCLE (n + 1)

INSTRUCTION

FETCH (S0)

EXECUTE (S1)

MRD

N0 - N2

N=1-9

ALLOWABLE MEMORY ACCESS

DATA BUS

ALLOWABLE MEMORY ACCESS

VALID OUTPUT

VALID DATA FROM MEMORY

DATA STROBE

(MRD • TPB • N)

(NOTE 1)

MEMORY READ CYCLE

MEMORY READ CYCLE

NOTE 1

USER GENERATED SIGNAL

“DON’T CARE” OR INTERNAL DELAYS

HIGH IMPEDANCE STATE

FIGURE 11. OUTPUT CYCLE TIMING WAVEFORMS

3-15

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