C8051F350 查看數據表（PDF） - Silicon Laboratories

零件编号

产品描述 (功能)

生产厂家

C8051F350

8 k ISP Flash MCU Family

Silicon Laboratories 

C8051F350/1/2/3

1.6. Programmable Comparator

C8051F350/1/2/3 devices include a software-configurable voltage comparator with an input multiplexer.

The Comparator offers programmable response time and hysteresis and two outputs that are optionally

available at the Port pins: a synchronous “latched” output (CP0), or an asynchronous “raw” output (CP0A).

Comparator interrupts may be generated on rising, falling, or both edges. When in IDLE mode, these inter-

rupts may be used as a “wake-up” source for the processor. Comparator0 may also be configured as a

reset source. A block diagram of the Comparator is shown in Figure 1.9.

VDD

Interrupt

Logic

Port I/O

Pins

+

-

GND

D SET Q

Q

CLR

D SET Q

Q

CLR

(SYNCHRONIZER)

Reset

Decision

Tree

CP0

(synchronous output)

CP0A

(asynchronous output)

Figure 1.9. Comparator0 Block Diagram

1.7. Serial Ports

The C8051F350/1/2/3 Family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud

rate configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hard-

ware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention.

26

Rev. 1.1

Share Link: