C8051F006 查看數據表（PDF） - Unspecified

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C8051F006

Mixed-Signal 32KB ISP FLASH MCU Family

Unspecified 

C8051F000/1/2/5/6/7

C8051F010/1/2/5/6/7

PRELIMINARY

Figure 20.9. PCA0MD: PCA Mode Register

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

CIDL

-

-

-

-

CPS1

CPS0

ECF

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xD9

Bit7:

CIDL: PCA Counter/Timer Idle Control.

Specifies PCA behavior when CPU is in Idle Mode.

0: PCA continues to function normally while the system controller is in Idle Mode.

1: PCA operation is suspended while the system controller is in Idle Mode.

Bits6-3: UNUSED. Read = 0000b, Write = don’t care.

Bits2-1: CPS1-CPS0: PCA Counter/Timer Pulse Select.

These bits select the timebase source for the PCA counter.

CPS1

0

0

1

1

CPS0

0

1

0

1

Timebase

System clock divided by 12

System clock divided by 4

Timer 0 overflow

High-to-low transitions on ECI (max rate = system clock divided by 4)

Bit0:

ECF: PCA Counter/Timer Overflow Interrupt Enable.

This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt.

0: Disable the CF interrupt.

1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is set.

4.2001; Rev. 1.3

CYGNAL Integrated Products, Inc.  2001

Page 159

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