74LV161DB 查看數據表（PDF） - Philips Electronics

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74LV161DB

Presettable synchronous 4-bit binary counter; asynchronous reset

Philips Electronics 

Philips Semiconductors

Presettable synchronous 4-bit binary counter;

asynchronous reset

Product specification

74LV161

FUNCTION TABLE

INPUTS

OUTPUTS

OPERATING MODES

MR

CP

CEP

CET

PE

Dn

Qn

TC

Reset (clear)

L

X

X

X

X

X

L

L

Parallel load

H

↑

X

X

I

I

L

L

H

↑

X

X

I

h

H

*

Count

H

↑

h

h

h

X

Count

*

Hold (do nothing)

H

X

I

X

h

X

qn

*

H

X

X

I

h

X

qn

L

NOTES:

* = The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH)

H = HIGH voltage level

h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition

L = LOW voltage level

I = LOW voltage level level one set-up time prior to the LOW-to-HIGH clock transition

q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition

X = don’t care

↑ = LOW-to-HIGH clock transition

STATE DIAGRAM

0

1

2

3

4

15

5

14

6

13

7

12

11

10

9

8

SV00573

TYPICAL TIMING SEQUENCE

MR

PE

D0

D1

D2

D3

CP

CEP

CET

Q0

Q1

Q2

Q3

TC

12 13 14 15 0 1 2

reset preset

count

inhibit

Typical timing sequence: reset outputs to zero; preset to binary twelve;

count to thirteen, fourteen, fifteen, zero, on and two; inhibit.

SV00574

1997 May 15

4

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