V54C333322V-55 查看數據表（PDF） - Mosel Vitelic Corporation

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V54C333322V-55

200/183/166 MHz 3.3 VOLT ULTRA HIGH PERFORMANCE 1M X 32 SDRAM 2 BANKS X 512Kbit X 32

Mosel Vitelic Corporation  

MOSEL VITELIC

V54C333322V

AC Characteristics (1,2,3) (Continued)

TA = 0 to 70°C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns

# Symbol Parameter

Read Cycle

25 tOH

27 tHZ

CAS Latency = 3

CAS Latency = 2

28 tDQZ

DQM Data Out Disable Latency

Write Cycle

29 tWR

Write Recovery Time

CAS Latency = 3

CAS Latency = 2

30 tDQW

DQM Write Mask Latency

-5

Min. Max.

2.5

–

–

5

–

7

2

–

5

–

10

–

0

–

Limit Values

-55

Min. Max.

2.5

–

–

5.3

–

7

2

–

5.5

–

10

–

0

–

-6

Min. Max.

2.5

–

–

5.5

–

7

2

–

6

–

10

–

0

–

Unit

ns

ns

CLK

ns

ns

CLK

Notes for AC Parameters:

1. For proper power-up see the operation section of this data sheet.

2. AC timing tests have VIL = 0.8V and VIH = 2.0V with the timing referenced to the 1.4 V crossover point. The transition

time is measured between VIH and VIL. All AC measurements assume tT = 1ns with the AC output load circuit

shown in Figure 1.

CLK

COMMAND

tCK

tCS tCH

1.4V

tAC

tLZ

VIH

VIL

tT

tAC

tOH

+ 1.4 V

50 Ohm

Z=50 Ohm

I/O

50 pF

OUTPUT

1.4V

tHZ

Figure 1.

3. If clock rising time is longer than 1 ns, a time (tT/2 – 0.5) ns has to be added to this parameter.

4. If tT is longer than 1 ns, a time (tT – 1) ns has to be added to this parameter.

5. These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as

follows:

the number of clock cycle = specified value of timing period (counted in fractions as a whole number)

6. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.

Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command

is registered.

V54C333322V Rev. 2.0 May 2000

11

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