AS4LC1M16S1-8TC 查看數據表（PDF） - Alliance Semiconductor

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AS4LC1M16S1-8TC

3.3V 2M × 8/1M × 16 CMOS synchronous DRAM

Alliance Semiconductor 

AS4LC2M8S1

AS4LC1M16S1

CLK

CMD

DQ

Write data

D0

Write recovery

CLK

CMD

Write data

DQ

D0

D1

D1

D2

Auto refresh waveform

CLK

tRP

CS

RAS

CAS

WE

A10

A0–A9

DQM

CKE

DQ

Precharge both banks Auto refresh

write cycle

tWR

D2

D3

tDPL

D3

PRE

ACT

Q4

tRP

(BL = 4)

tRP

PRE

ACT

tDAL

This precharge is implicit in case of Auto-P Write.

tRC

tRC

Auto refresh

Auto refresh

22

ALLIANCE SEMICONDUCTOR

7/5/00

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