AS4LC1M16S1-8TC 查看數據表（PDF） - Alliance Semiconductor

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AS4LC1M16S1-8TC

3.3V 2M × 8/1M × 16 CMOS synchronous DRAM

Alliance Semiconductor 

AS4LC2M8S1

AS4LC1M16S1

Write—full-page burst

CLK

T0

tCKS tCKH

tCL T1

tCH

CKE

tCK*†ƒ T2

T3

T4

T5

Tn+1

Tn+2

tCMS tCMH

COMMAND ACTIVE

DQM†

NOP

WRITE

NOP

NOP

NOP

tCMS tCMH

NOP

BURST TERM

A0–A9

tAS tAH

ROW

C(oAl0u-mAn7)m*

A10

BA

tAS tAH

ROW

tAS tAH

BANK

DQ

BANK

tDS

tDH

tDS tDH

tDS tDH

tDS tDH

tDS tDH

tDS tDH

tRCD

DIN m

DIN m+1

DIN m+2

DIN m+3

256 locations within same row

DIN m+255

Full page completed

Full-page burst does not

self terminate. Can use

ƒ

BURST TERMINATE command.

* A8 and A9 = Don’t care.

† DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.

ƒPage left open; no tRP.

Tn+3

NOP

Read—full-page burst*

T0

T1

T2

T3

CLK

tCL

tCK

tCH

tCMS tCMH

CKE

T4

T5

T6

Tn+1

Tn+2

Tn+3

tCMS tCMH

ACTIVE

NOP

READ

NOP

NOP

NOP

NOP

NOP

BURST

TERM

NOP

Command

Tn+4

NOP

DQM†

tAS

tAH

A0–A9 ROW

tAS tAH

A10 ROW

C(OAL0U-AM7N)†m

tAS tAH

BA

BANK

BANK

DQ

tRCD

tAC*†ƒ

tLZ

CAS Latency

tAC*†ƒ

tOH

tAC*†ƒ

tOH

tAC*†ƒ

tOH

DOUT m

DOUT m+1

DOUT m+2

256 locations within same row

tAC*†ƒ

tOH

DOUT m+255

Full page completed

* For this example, the CAS latency = 2.

† A8 and A9 = “Don’t care.”

ƒ DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.

** Page left open; no tRP.

tAC*†ƒ

tOH

DOUT m

tOH

DOUT m+1

tHZ*†ƒ

Full-page burst does not self-terminate.**

Can use BURST TERMINATE command.

14

ALLIANCE SEMICONDUCTOR

7/5/00

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