BD8964FVM
Datasheet
(3) Selection of input capacitor (CIN)
Input capacitor must be a low ESR capacitor with a capacitance sufficient to
cope with high ripple current to prevent high transient voltage. The ripple current
VCC
CIN
IRMS is given by the equation (5):
VOUT
L
CO
Figure 28. Input Capacitor
IRMS IOUT
VOUT VCC VOUT
VCC
A・・・(6)
< Worst case > IRMSMax
When
VCC
is twice
the
VOUT , IRMS
IOUT
2
If VCC=5.0V, VOUT=1.5V, and IOUTMax=0.8A
IRMS 0.8
1.55 1.5 0.37
5
ARMS
A low ESR 10μF/10V ceramic capacitor is recommended to reduce ESR dissipation of input capacitor for better
efficiency.
(4) Calculating RITH, CITH for Phase Compensation
Since the Current Mode Control is designed to limit the inductor current, a pole (phase lag) appears in the low
frequency area due to a CR filter consisting of the output capacitor and the load resistance, while a zero (phase lead)
appears in the high frequency area due to the output capacitor and its ESR. Therefore, the phases are easily
compensated by adding a zero to the power amplifier output with C and R as described below to cancel a pole at the
power amplifier.
A
Gain
[dB]
0
0
Phase
[deg]
-90
A
Gain
[dB]
0
0
Phase
[deg]
-90
fp(Min)
fp(Max)
IOUTMin
IOUTMax
fZ(ESR)
fp
2
1
RO
CO
fZ ESR
2
1
ESR
CO
Pole at power amplifier
When the output current decreases, the load resistance RO
increases and the pole frequency decreases.
Figure 29. Open Loop Gain Characteristics
fZ(Amp)
fpMin
2
1
ROMax
Co
fpMax
2
1
RO MIN
Co
Hz with lighter load
Hz with heavier load
Zero at power amplifier
Increasing the capacitance of the output capacitor lowers the
pole frequency while the zero frequency does not change.
(This is because when the capacitance is doubled, the
capacitor ESR is reduced to half.)
fZ Amp
2
1
RITH
CITH
Figure 30. Error Amp Phase Compensation Characteristics
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22.Jan.2015 Rev.003