MAX117EAI 查看數據表（PDF） - Maxim Integrated
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MAX117EAI Datasheet PDF : 12 Pages
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+3V, 400ksps, 4/8-Channel,
8-Bit ADCs with 1µA Power-Down
______________________________________________________________Pin Description
PIN
MAX113 MAX117
—
1
—
2
1
3
2
4
3
5
4
6
5
7
6
7, 8, 9
10
11
12
13
8
9, 10, 11
12
13
14
15
14
16
15
16
17, 18, 19
20
—
21
22
23
24
—
17
18
19, 20, 21
22
23
24
25
26
27
28
NAME
IN6
IN5
IN4
IN3
IN2
IN1
MODE
D0
D1, D2, D3
RD
INT
GND
REF-
REF+
WR/RDY
CS
D4, D5, D6
D7
A2
A1
A0
PWRDN
VDD
IN7
FUNCTION
Analog Input Channel 6
Analog Input Channel 5
Analog Input Channel 4
Analog Input Channel 3
Analog Input Channel 2
Analog Input Channel 1
Mode Selection Input. Internally pulled low with a 15µA current source. MODE = 0
activates read mode; MODE = 1 activates write-read mode (see Digital Interface
section).
Three-State Data Output (LSB)
Three-State Data Outputs
Read Input. RD must be low to access data (see Digital Interface section).
Interrupt Output. INT goes low to indicate end of conversion (see Digital Interface
section).
Ground
Lower limit of reference span. REF- sets the zero-code voltage. Range is GND ≤
VREF- < VREF+.
Upper limit of reference span. REF+ sets the full-scale input voltage. Range is
VREF- < VREF+ ≤ VDD. Internally hardwired to IN8 (Table 1).
Write-Control Input/Ready-Status Output (see Digital Interface section)
Chip-Select Input. CS must be low for the device to recognize WR or RD inputs.
Three-State Data Outputs
Three-State Data Output (MSB)
Multiplexer Channel Address Input (MSB)
Multiplexer Channel Address Input
Multiplexer Channel Address Input (LSB)
Power-Down Input. PWRDN reduces supply current when low.
Positive Supply, +3.0V to +3.6V
Analog Input Channel 7
6 _______________________________________________________________________________________
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